Semiconductor memory devices are disclosed, and more particularly, a voltage generator for generating a stable cell plate voltage with improved drivability of an output driver in a semiconductor memory device is disclosed.
In general, a bit line precharge voltage Vblp for precharging a bit line in a DRAM device has a voltage level somewhere between a high voltage data signal and a low voltage data signal, which is stored in a DRAM cell. The bit line precharge voltage Vblp is xc2xd of the value of the voltage stored in the DRAM cell, thereby minimizing the power consumption in an equalization operation.
The cell plate voltage Vcp is a voltage applied to a reference terminal of a DRAM cell capacitor and is equivalent to xc2xd of the value, (xc2xd*Vcc), of the bit line precharge voltage Vblp. The cell plate voltage Vcp is used to ensure the reliability of the DRAM cell capacitor by supplying xc2xd*Vcc between both terminals of the DRAM cell capacitor regardless of the data voltage stored in the DRAM cell.
FIG. 1 is an exemplary circuit diagram of a prior art cell plate voltage generator. The circuit of FIG. 1 is applicable to a bit line precharge voltage generator. Referring to FIG. 1, the cell plate voltage generator includes a voltage divider 10, a bias voltage generator 20, a gate voltage generator 30, an output voltage controller 40 and an output driver 50.
The voltage divider 10 includes resistors R1 and R2 connected in series to an internal power supply voltage Vcc and a ground voltage Vss, and in cases where an internal power supply voltage Vcc is externally supplied, divides the internal power supply voltage Vcc to generate a cell plate reference voltage Vcp_ref.
The bias voltage generator 20 includes a PMOS transistor P1 wherein the cell plate reference voltage Vcp_ref is supplied to its gate, and a PMOS transistor P2 and NMOS transistors N1 and N2, configured in a current-mirror manner. The bias voltage generator 20 generates an n-bias voltage Nbias to enable a constant current flow to the ground voltage Vss, and a p-bias voltage Pbias to enable a constant current flow from an internal power supply voltage Vcc.
The gate voltage generator 30 includes PMOS transistors P3 and P4, and NMOS transistors N3 and N4, configured in a current-mirror manner. The gate voltage generator 30 generates an n-gate voltage Ngate that is higher, by a threshold voltage Vt of the NMOS transistor N3, than the cell plate reference voltage Vcp_ref. The gate voltage generator 30 also generates a p-gate voltage Pgate that is lower, by a threshold voltage Vt of the PMOS transistor P4, than the cell plate reference voltage Vcp_ref.
The output voltage controller 40 includes PMOS transistors P5 and P6, and NMOS transistors N5 and N6, connected in series between the internal power supply voltage Vcc and the ground voltage Vss. The p-bias voltage Pbias is applied to a gate of the PMOS transistors P5. The p-gate voltage Pgate is applied to a gate of PMOS transistor P6. The n-gate voltage Ngate is applied to an NMOS transistor N5. The n-bias voltage Nbias is applied to a gate of NMOS transistor N6. The output voltage controller 40 generates a pull-up signal PU and a pull-down signal PD.
The output driver 50 includes a PMOS transistor P7, and an NMOS transistor N7, that are connected between the internal power supply voltage Vcc and the ground voltage Vss. The output driver 50 generates a cell plate voltage Vcp. The pull-up signal PU is provided to a gate of the PMOS transistor P7 while the pull-down signal PD is provided to a gate of the NMOS transistor N7.
The NMOS transistors N1, N2, N4 and N6 receive the n-bias voltage Nbias and flow a constant current with a slight variation to the ground voltage Vss. The PMOS transistors P2, P3 and P5 receive the p-bias voltage Pbias and flow a constant current with a slight variation to the internal power supply voltage Vcc. The n-gate bias Ngate is selected in order to ensure a constant current flow to the PMOS transistor P3 and the NMOS transistor N3 of the n-gate voltage generator 30 in an equilibrium state.
If the cell plate voltage Vcp is higher than the cell plate reference voltage Vcp_ref, the current flowing to the NMOS transistor N5 is decreased and the voltage of the pull-up signal PU is increased, thereby causing the PMOS transistor P7 to turn off. If, however, the cell plate voltage Vcp is lower than the cell plate reference voltage Vcp_ref, the current flowing to the NMOS transistor N5 is increased and the voltage of the pull-up signal PU is decreased, thereby causing the PMOS transistor P7 to turn on.
Referring to the cell plate voltage generator illustrated in FIG. 1, if the cell plate voltage Vcp is set to a value substantially near xc2xd*Vcc, the voltage of the pull-up signal PU swings between the internal power supply voltage Vcc and xc2xd*Vcc while the voltage of the pull-down signal PD swings between xc2xd*Vcc and the ground voltage Vss.
At this time, if the internal power supply voltage Vcc is lowered, the cell plate voltage Vcp is lower than the threshold voltage Vt. Then, the PMOS transistor P7 is not sufficiently turned on. Similarly, the phenomenon may occur in the NMOS transistor P7. Because the threshold voltage of the PMOS transistor is higher relative to that of the NMOS transistor, and the current drivability of the PMOS transistor is lower than that of the NMOS transistor in the same size and the problem generally occurs in the pull-up device in advance.
FIG. 2 is a graph illustrating the resultant value of the voltages of FIG. 1. FIG. 3 shows the current waveform of the cell plate voltage Vcp in FIG. 1, which is a simulation graph of the current drivability of the cell plate voltage Vcp in 0.13 xcexcm technology where the temperature is 0xc2x0 and the power voltage is 1.5V.
In general, it is estimated that the cell plate voltage Vcp is maintained at xc2xd*1.5V, and that at 0.75V, no voltage variation in the output stage exists in a standby state. However, in the case where the current consumption of the cell plate voltage Vcp is in the range of xc2x14 mA, the cell plate voltage Vcp drops to 0.3V as shown in FIG. 3. As a result, when the voltage of the pull-up signal PU swings between the internal power supply voltage Vcc and xc2xd*Vcc and the voltage of the pull-down signal PD swings between xc2xd*Vcc and the ground voltage, and if the power supply voltage is lowered, then the cell plate voltage Vcp is also lowered. However, because the threshold voltage Vt of the transistor is not lowered in proportion to the cell plate voltage Vcp, and if the cell plate voltage Vcp is lower than the threshold voltage Vt of the transistor, then the output driver of the cell plate voltage generator is not sufficiently driven.
A voltage generator is disclosed which improves the drivability of an output driver and to ensure a stable cell plate voltage by controlling a gate signal of the output driver in a cell plate voltage generator to swing between a power supply voltage and a ground voltage.
Thus, an improved voltage generator for a semiconductor memory device is provided. The disclosed voltage generator includes an output voltage controller to generate a pull-up signal and a pull-down signal for controlling a pull-down operation, the pull-up signal having a level substantially equivalent to a power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, the pull-up signal having a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage. The voltage generator also includes an output driver to generate a stable cell plate voltage in response to the pull-up signal and the pull-down signal.
In an embodiment, the voltage generator may include an output voltage controller to generate a pull-up control signal and a pull-down control signal, the pull-up control signal having a level substantially equivalent to a power supply voltage if a cell plate voltage is higher than a cell plate reference voltage, and a level below the cell plate voltage if the cell plate voltage is lower than the cell plate reference voltage, and the pull-down control signal having a level above the cell plate voltage if the cell plate voltage is higher than the cell plate reference voltage and a level substantially equivalent to a ground voltage if the cell plate voltage is lower than the cell plate reference voltage. The voltage generator also includes an output driver to generate a stable cell plate voltage in response to the pull-up control signal and the pull-down control signal.